The present invention relates to a picture display memory system and in particular to a picture display memory circuit which is suitable to write data into a picture memory at high speed.
In a picture display memory system for reading out picture information stored in a memory and for graphically displaying the picture information on a screen such as a cathode ray tube (hereinafter abbreviated as CRT), LCD or plasma display, the amount of information per dot of pixel tends to increase for displaying a more natural picture. Thus, a picture memory having a large capacity is needed and it takes much time to write data.
FIG. 1 shows an example of the bit configuration in such a conventional picture memory. The display screen is divided into 320 pixels (dots) in the horizontal direction and is divided into 200 lines in the vertical direction. For each pixel (dot), four bits of information are assigned to each of three primary colors R (red), G (green) and B (blue). As illustrated in FIG. 2, the picture information of one pixel is subjected to D/A conversion for each of the primary colors R, G and B to feed analog R, G and B signals to a CRT. Thus, each pixel (dot) of display can be colored in 2.sup.12 =4,096 possible ways. As a result, it becomes possible to reproduce a natural picture which compares favorably with a picture derived from a conventional analog video signal.
FIG. 3A shows an example of a method for writing picture information into the picture memory illustrated in FIG. 1.
In the example illustrated in FIG. 3A, the picture memory is divided into blocks, each of which is .DELTA.X in horizontal length, .DELTA.Y in vertical length and .DELTA.Z in depth. In one block, the picture data of pixels are successively written into the picture memory using the sequential line scanning method starting from the upper left pixel located on the X-Y plane corresponding to the screen toward the lower right pixel, as illustrated in FIG. 3A. For writing data at high speed, addresses are assigned in the picture memory as illustrated in FIG. 3B. Data bits D.sub.0 to D.sub.11 representing the color information are assigned to locations in the Z direction of the memory space corresponding to the display screen, i.e., in the depth direction at a dot position. And the addresses of the picture memory are assigned to respective pixels. It is advantageous to use writing by a central processing unit (hereafter abbreviated as CPU) in the above-described addressing method.
The manner of writing picture data into the picture memory having addresses assigned as described above will now be described by referring to a picture memory circuit illustrated in FIG. 4. In FIG. 4, a data bus 1, an address bus 2 and a write control signal 3 are coupled to the CPU. Address selection signals 6a and 6b are supplied from an address decoder 5 to a picture memory 4a and an address register 9, respectively. A write control circuit 8a composed of NAND gates controls inputs to each chip of the picture memory 4a responsive to the write control signal 3 fed from the CPU.
In the picture memory 4a, 12 bits arranged in the depth direction of the display screen are assigned to each memory chip as illustrated in FIG. 3B. The infcrmation for designating a bit pattern to be written into the picture memory 4 is stored into the address register 9 by the CPU beforehand. The write control circuit 8a supplies AND outputs of the bit pattern stored in the register 9 and the write control signal 3 fed from the CPU to each chip of the picture memory 4a. When data is to be writen into a specified address of the picture memory 4a, therefore, data is written into addressed bit positions of the picture memory according to the bit pattern stored in the register 9.
Even if data is written into blocks one after another as illustrated in FIG. 3A, logical ORing by means of software is not required when data at a different bit position must be overwritten at an address of the picture memory 4a having data already written thereon. It is necessary only to write the added data irto the picture memory 4a provided that the information designating the bit positions in which data is to be written is stored into the register 9 beforehand.
In the picture memory circuit of the prior art illustrated in FIG. 4, however, an address of the picture memory is assigned to a setof data bits arranged in the depth direction. In addition, the CPU can designate an address only for each pixel. When a consecutive picture pattern must be written in the horizontal direction of the display screen for the purpose of reading a character pattern stored in a ROM to transfer it to the picture memory, therefore, the picture pattern continuing in the horizontal direction must be divided into data bits and thereafter the picture information composed of the color information and graduation information must be written in the depth direction for each pixel. This results in a problem that an excessively long processing time is required.